The present invention relates to memories which allow simultaneous read and write operations per cycle while using single-ported memory banks.
In a shared memory switch, one of the bottlenecks that limits the switch's bandwidth is the speed of the memory. In the worst case, a particular memory location may need to be written and read on every packet. Therefore, to have a fully-provisioned switch for a given bandwidth using single-ported static random access memory (SRAM) cells, the operating speed of the memory must be twice as fast as the desired packet-rate.
Alternatively, the required speed of the memory may be cut in half by using dual-ported SRAM cells which allow two operations (i.e., a read and a write) per cycle. However, this requires as much as two times the silicon area compared to a single ported SRAM.